verilog-basics-for-lowlevel

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Verilog Basics for Low-Level Engineers

面向底层工程师的 Verilog 基础

Purpose

目的

Give firmware and kernel engineers enough Verilog/SystemVerilog literacy to read RTL: modules, clocks/resets, combinational vs sequential logic, bus interfaces, and why hardware behavior explains driver bugs — not a replacement for HDL design courses.

让 firmware 和 kernel 工程师具备足够的 Verilog/SystemVerilog 素养，以便阅读 RTL：理解 modules、clocks/resets、组合逻辑与时序逻辑、bus interfaces，以及 hardware 行为为何能够解释 driver bugs；本 skill 不能替代 HDL design 课程。

When to Use

何时使用

Reference manual unclear — RTL clarifies register behavior
Understanding CDC (clock domain crossing) bugs
Correlating DMA/AXI transactions with driver ordering
Reviewing SoC block diagram with hardware team

Reference manual 含义不清——通过 RTL 厘清 register 行为
理解 CDC（clock domain crossing）bugs
将 DMA/AXI transactions 与 driver ordering 关联起来
与 hardware 团队一起审查 SoC block diagram

Workflow

工作流程

1. Module structure

1. Module 结构

verilog

module uart_tx (
    input  wire       clk,
    input  wire       rst_n,   /* active-low async reset */
    input  wire       start,
    input  wire [7:0] data,
    output reg        busy
);
    /* sequential logic */
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            busy <= 1'b0;
        else if (start)
            busy <= 1'b1;
        /* ... */
    end
endmodule

wire

= combinational/network;

reg

always

block = flip-flop unless combinational

always @(*)

verilog

module uart_tx (
    input  wire       clk,
    input  wire       rst_n,   /* active-low async reset */
    input  wire       start,
    input  wire [7:0] data,
    output reg        busy
);
    /* sequential logic */
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            busy <= 1'b0;
        else if (start)
            busy <= 1'b1;
        /* ... */
    end
endmodule

wire

= 组合逻辑/网络；在

always

block 中使用

reg

= flip-flop，除非是组合逻辑

always @(*)

。

2. Synthesizable subset (what firmware folks need)

2. 可综合子集（firmware 工程师所需内容）

Construct	Meaning
`posedge clk`	Registered update
`assign x = a & b`	Combinational
`case` / `if` in `always @(*)`	Mux logic
Parameters `#(.WIDTH(32))`	Configurable width

Avoid

#delay

in synthesizable RTL — simulation only.

构造	含义
`posedge clk`	寄存器式更新
`assign x = a & b`	组合逻辑
`always @(*)` 中的 `case` / `if`	Mux 逻辑
参数 `#(.WIDTH(32))`	可配置位宽

避免在可综合 RTL 中使用

#delay

——它仅用于 simulation。

3. Reset discipline

3. Reset 规范

Async assert, sync deassert common (
```
rst_sync_n
```
)
Firmware must wait post-reset setup times — see RM reset chapter
Multiple reset domains → peripheral may need explicit soft reset bit

异步 assert、同步 deassert 很常见（
```
rst_sync_n
```
）
Firmware 必须等待 reset 后的 setup times——参见 RM 的 reset 章节
存在多个 reset domains → peripheral 可能需要显式的 soft reset bit

4. Bus protocols (reading SoC diagrams)

4. Bus protocols（阅读 SoC diagrams）

Bus	Typical use
APB	Slow peripherals, simple reg interface
AHB	Higher throughput on-chip
AXI	DMA, modern SoCs — bursts, channels

Linux

regmap

MMIO maps to APB/AXI slave decode in RTL address map.

总线	典型用途
APB	慢速 peripherals、简单的 reg interface
AHB	芯片内更高吞吐量
AXI	DMA、现代 SoC——bursts、channels

在 Linux 中，

regmap

MMIO 会映射到 RTL address map 中的 APB/AXI slave decode。

5. Clock domains

Signals crossing

clk_a

→

clk_b

need synchronizers (2+ FFs). Metastability causes intermittent firmware bugs — not fixed in software alone.

从

clk_a

→

clk_b

跨越的 signals 需要 synchronizer（2 个或更多 FFs）。Metastability 会导致间歇性 firmware bugs——无法仅通过 software 修复。

6. Simulation vs silicon

6. Simulation 与 silicon

bash

undefined

bash

undefined

Typical open-source sim (conceptual)

iverilog -o sim.vvp design.v tb.v vvp sim.vvp


QEMU/peripheral models may not match RTL edge cases.

iverilog -o sim.vvp design.v tb.v vvp sim.vvp


QEMU/peripheral models 可能无法与 RTL edge cases 完全匹配。

7. Agent usage

7. Agent 使用方式

/verilog-basics-for-lowlevel Explain this APB register block and when STATUS bit updates relative to WRITE

/verilog-basics-for-lowlevel Explain this APB register block and when STATUS bit updates relative to WRITE

Common Problems

常见问题

Symptom	Cause	Fix
Bit toggles once	Pulse in RTL	Poll latch / clear-on-read in driver
Random corruption	CDC	Hardware synchronizer; don't hack delays
Read stale data	Bus bridge buffer	Follow RM ordering / barrier
IRQ stuck	Level vs pulse in RTL	Match handler ACK sequence
Verilog vs VHDL	Mixed SoC docs	Focus on interface signals table

症状	原因	修复方法
Bit 只翻转一次	RTL 中的 Pulse	在 driver 中轮询 latch / 使用 clear-on-read
随机数据损坏	CDC	使用 hardware synchronizer；不要用 delay 变通
读取到 stale data	Bus bridge buffer	遵循 RM ordering / barrier
IRQ 卡住	RTL 中为 level 而非 pulse	匹配 handler 的 ACK sequence
Verilog 与 VHDL 混用	混合的 SoC docs	聚焦 interface signals 表

verilog-basics-for-lowlevel

Original

Translation

Verilog Basics for Low-Level Engineers

面向底层工程师的 Verilog 基础

Purpose

目的

When to Use

何时使用

Workflow

工作流程

1. Module structure

1. Module 结构

2. Synthesizable subset (what firmware folks need)

2. 可综合子集（firmware 工程师所需内容）

3. Reset discipline

3. Reset 规范

4. Bus protocols (reading SoC diagrams)

4. Bus protocols（阅读 SoC diagrams）

5. Clock domains

5. Clock domains

6. Simulation vs silicon

6. Simulation 与 silicon

Typical open-source sim (conceptual)

Typical open-source sim (conceptual)

7. Agent usage

7. Agent 使用方式

Common Problems

常见问题

Related Skills

相关 Skills