eda-schematics

Compare original and translation side by side

🇺🇸

Original

English

🇨🇳

Translation

Chinese

EDA Schematics Skill

EDA原理图Skill

Create and wire schematics for electronics projects.

为电子项目创建并布线原理图。

Auto-Activation Triggers

自动激活触发条件

This skill activates when:

User asks to "create schematic", "add component", "wire"
User is working with
```
.kicad_sch
```
files
User asks about net names, connections, or ERC
Project has component selections but no schematic
User mentions schematic organization or sheets

当满足以下条件时，该Skill会激活：

用户要求“创建原理图”、“添加元件”、“布线”
用户正在处理
```
.kicad_sch
```
文件
用户询问网络名称、连接或ERC相关问题
项目已选择元件但未创建原理图
用户提及原理图组织或图纸相关内容

Context Requirements

上下文要求

Requires:

```
docs/component-selections.md
```
- Selected components with LCSC numbers
```
docs/design-constraints.json
```
- Project constraints
```
datasheets/
```
- Component datasheets for reference circuits

Produces:

```
hardware/*.kicad_sch
```
- KiCad schematic file(s)
```
docs/schematic-status.md
```
- Status and progress tracking

需要：

```
docs/component-selections.md
```
- 带有LCSC编号的已选元件
```
docs/design-constraints.json
```
- 项目约束条件
```
datasheets/
```
- 用于参考电路的元件datasheet

产出：

```
hardware/*.kicad_sch
```
- KiCad原理图文件
```
docs/schematic-status.md
```
- 状态与进度跟踪文档

Workflow

工作流程

1. Load Context

1. 加载上下文

@docs/design-constraints.json
@docs/component-selections.md
@datasheets/ (relevant datasheets)

From design-constraints.json, extract:

```
power.topology
```
- LDO vs buck affects schematic complexity
```
power.rails[]
```
- All voltage rails to implement
```
board.layers
```
- 2-layer = simpler designs, 4+ = can be more complex
```
thermal.budget
```
- Identify hot components for grouping
```
dfmTargets.assembly
```
- Package sizes must match

@docs/design-constraints.json
@docs/component-selections.md
@datasheets/ (相关datasheet)

从design-constraints.json中提取：

```
power.topology
```
- LDO与降压拓扑会影响原理图复杂度
```
power.rails[]
```
- 需要实现的所有电压轨
```
board.layers
```
- 2层板=设计更简单，4层及以上=可支持更复杂设计
```
thermal.budget
```
- 识别需要分组的发热元件
```
dfmTargets.assembly
```
- 封装尺寸必须匹配

1.5. Validate Readiness

1.5. 就绪性验证

Before starting schematic:

All required components selected in
```
component-selections.md
```
?
MCU selected with known pinout?
Voltage regulators selected?
Critical passives (decoupling values) defined?
Datasheets downloaded for reference circuits?

If not, suggest running

/eda-source [role]

first.

开始绘制原理图前：

```
component-selections.md
```
中是否已选择所有必需元件？
是否已选择具有已知引脚定义的MCU？
是否已选择电压调节器？
是否已定义关键无源器件（去耦电容值）？
是否已下载用于参考电路的datasheet？

如果未满足，建议先运行

/eda-source [role]

。

2. Plan Sheet Organization

2. 规划图纸组织结构

See

reference/SCHEMATIC-HIERARCHY-DECISION.md

for detailed guidance.

Based on complexity, organize into sheets:

Simple design (1-2 sheets):

Sheet 1: Everything

Medium design (3-4 sheets):

Sheet 1: Power (input, regulators)
Sheet 2: MCU and core logic
Sheet 3: Interfaces and I/O

Complex design (5+ sheets):

Sheet 1: Power input and protection
Sheet 2: Voltage regulation
Sheet 3: MCU and clock
Sheet 4: Communication interfaces
Sheet 5: Connectors and I/O
Additional sheets as needed

详细指导请参考

reference/SCHEMATIC-HIERARCHY-DECISION.md

。

根据设计复杂度，将原理图组织为多张图纸：

简单设计（1-2张图纸）：

图纸1：包含所有内容

中等设计（3-4张图纸）：

图纸1：电源（输入、调节器）
图纸2：MCU与核心逻辑
图纸3：接口与I/O

复杂设计（5张及以上图纸）：

图纸1：电源输入与保护
图纸2：电压调节
图纸3：MCU与时钟
图纸4：通信接口
图纸5：连接器与I/O
根据需要添加额外图纸

3. Create Schematic Structure

3. 创建原理图结构

Create main schematic file
Add hierarchical sheets if multi-sheet
Set up page sizes and title blocks

创建主原理图文件
若为多图纸设计，添加分层图纸
设置页面尺寸与标题栏

4. Place Components (Per Sheet)

4. 放置元件（按图纸）

For each component:

Place symbol from library
Set reference designator
Set value
Add LCSC part number to properties
Position logically

Tool syntax:

mcp__kicad-sch__add_component schematic_path="/path/to/file.kicad_sch" lib_id="EDA-MCP:SymbolName" reference="U1" value="10k" position=[100, 100]

Use
```
symbol_ref
```
from
```
library_fetch
```
response (e.g.,
```
EDA-MCP:ESP32-C3
```
)
For standard parts, use KiCad libraries (e.g.,
```
Device:R
```
,
```
Device:C
```
)
Position uses grid-aligned coordinates (1.27mm grid)

Placement guidelines:

Power flows top-to-bottom or left-to-right
Signal flows left-to-right
Group related components
Leave space for wiring

针对每个元件：

从库中放置元件符号
设置参考编号
设置参数值
在属性中添加LCSC部件编号
合理布局位置

工具语法：

mcp__kicad-sch__add_component schematic_path="/path/to/file.kicad_sch" lib_id="EDA-MCP:SymbolName" reference="U1" value="10k" position=[100, 100]

使用
```
library_fetch
```
响应中的
```
symbol_ref
```
（例如：
```
EDA-MCP:ESP32-C3
```
）
标准器件使用KiCad库（例如：
```
Device:R
```
,
```
Device:C
```
）
位置使用网格对齐坐标（1.27mm网格）

布局指南：

电源流向为从上到下或从左到右
信号流向为从左到右
相关元件分组放置
为布线预留空间

5. Add Power Symbols

5. 添加电源符号

Place VCC symbols for each rail
Place GND symbols
Use consistent power symbol naming

为每个电压轨放置VCC符号
放置GND符号
使用统一的电源符号命名规则

6. Wire Connections

6. 布线连接

Follow the reference circuits from datasheets:

Wire power connections first
Add decoupling capacitors to power pins
Wire critical signals (crystal, reset)
Wire communication buses
Wire remaining signals

Use net labels for:

Inter-sheet connections
Buses
Avoiding wire crossing
Named signals (for clarity)

参考datasheet中的电路进行布线：

优先连接电源
为电源引脚添加去耦电容
连接关键信号（晶振、复位）
连接通信总线
连接剩余信号

以下场景使用网络标签：

跨图纸连接
总线
避免线路交叉
命名信号（提升可读性）

7. Verify and Document

7. 验证与文档记录

Check all pins connected or marked NC
Run ERC (electrical rules check)
Document status

See

reference/ERC-VIOLATIONS-GUIDE.md

for fixing common ERC errors.

检查所有引脚是否已连接或标记为NC
运行ERC（电气规则检查）
记录状态

修复常见ERC错误请参考

reference/ERC-VIOLATIONS-GUIDE.md

。

8. Pre-Layout Review

8. 布局前评审

Before proceeding to layout, complete

reference/SCHEMATIC-REVIEW-CHECKLIST.md

Power section verification
Decoupling validation
Interface protection check
Test points present
Net naming consistency
Documentation complete

进入布局阶段前，完成

reference/SCHEMATIC-REVIEW-CHECKLIST.md

中的检查项：

电源部分验证
去耦电容有效性验证
接口保护检查
测试点是否存在
网络命名一致性
文档是否完整

Net Naming Convention

网络命名规范

See

reference/NET-NAMING.md

for complete conventions.

Quick reference:

Power:    VCC_3V3, VCC_5V, VBAT, GND, GNDA
Reset:    MCU_RESET, nRESET
SPI:      SPI1_MOSI, SPI1_MISO, SPI1_SCK, SPI1_CS
I2C:      I2C1_SDA, I2C1_SCL
UART:     UART1_TX, UART1_RX
GPIO:     LED_STATUS, BTN_USER, or GPIO_PA0

完整规范请参考

reference/NET-NAMING.md

。

快速参考：

Power:    VCC_3V3, VCC_5V, VBAT, GND, GNDA
Reset:    MCU_RESET, nRESET
SPI:      SPI1_MOSI, SPI1_MISO, SPI1_SCK, SPI1_CS
I2C:      I2C1_SDA, I2C1_SCL
UART:     UART1_TX, UART1_RX
GPIO:     LED_STATUS, BTN_USER, or GPIO_PA0

Output Format

输出格式

schematic-status.md

markdown

undefined

markdown

undefined

Schematic Status

原理图状态

Project: [name] Updated: [date]

项目: [名称] 更新时间: [日期]

Summary

摘要

Total sheets: X
Components placed: Y
Wiring: Z% complete
ERC: X errors, Y warnings

总图纸数: X
已放置元件数: Y
布线完成度: Z%
ERC检查: X个错误, Y个警告

Sheets

图纸详情

Sheet 1: Power

图纸1: 电源

Status: Complete
Components: U1 (regulator), C1-C4 (caps)
Notes: ...

状态: 已完成
元件: U1(调节器), C1-C4(电容)
备注: ...

Sheet 2: MCU

图纸2: MCU

Status: In Progress
Components: U2 (MCU), Y1 (crystal), C5-C10
Notes: Needs clock wiring

状态: 进行中
元件: U2(MCU), Y1(晶振), C5-C10
备注: 需完成时钟布线

ERC Issues

ERC问题

Unconnected pin on U2.PA3 (intentional NC)
Missing power flag (fixed)

U2.PA3引脚未连接（为有意NC）
缺少电源标识（已修复）

Next Steps

下一步计划

Complete MCU clock circuit
Wire SPI bus to flash
Run final ERC

undefined

完成MCU时钟电路
连接SPI总线至闪存
运行最终ERC检查

undefined

Guidelines

设计指南

Always check datasheets for reference circuits
Place decoupling caps within 3mm of IC power pins (in layout)
Use net labels for any signal that crosses sheets
Keep schematic readable - avoid wire spaghetti
Add notes for non-obvious connections
Mark intentionally unconnected pins with NC flag

始终参考datasheet中的参考电路
去耦电容需放置在IC电源引脚3mm范围内（布局阶段）
跨图纸的信号需使用网络标签
保持原理图可读性，避免线路杂乱
为非直观连接添加备注
有意未连接的引脚标记为NC

Architecture Validation Warnings

架构验证警告

Check these before proceeding to layout:

Condition	Warning
Buck converter selected but no inductor in schematic	Missing critical component
USB interface but no ESD protection	Add ESD diodes before layout
External connector but no protection	Add TVS/ESD on exposed signals
MCU with <100nF per VDD pin	Verify decoupling against datasheet
Crystal but no load cap calculation	Recalculate CL values
I2C bus but no pull-ups	Add pull-ups (4.7K-10K)
SPI CS lines floating	Add pull-ups to prevent glitches
Reset pin without RC debounce	Add debounce circuit

进入布局阶段前请检查以下内容：

条件	警告
选择了降压转换器但原理图中无电感	缺少关键元件
有USB接口但无ESD保护	布局前添加ESD二极管
有外部连接器但无保护	在暴露信号上添加TVS/ESD器件
MCU的每个VDD引脚对应的电容小于100nF	根据datasheet验证去耦配置
有晶振但未计算负载电容	重新计算CL值
有I2C总线但无上拉电阻	添加4.7K-10K的上拉电阻
SPI的CS引脚浮空	添加上拉电阻防止干扰
复位引脚无RC防抖电路	添加防抖电路

Reference Documents

参考文档

Document	Purpose
`reference/NET-NAMING.md`	Net naming conventions
`reference/SYMBOL-ORGANIZATION.md`	Schematic layout patterns
`reference/REFERENCE-CIRCUITS.md`	Common circuit patterns
`reference/SCHEMATIC-HIERARCHY-DECISION.md`	Sheet organization guidance
`reference/SCHEMATIC-REVIEW-CHECKLIST.md`	Pre-layout validation
`reference/ERC-VIOLATIONS-GUIDE.md`	Fixing ERC errors

文档	用途
`reference/NET-NAMING.md`	网络命名规范
`reference/SYMBOL-ORGANIZATION.md`	原理图布局模式
`reference/REFERENCE-CIRCUITS.md`	常见电路模式
`reference/SCHEMATIC-HIERARCHY-DECISION.md`	图纸组织指南
`reference/SCHEMATIC-REVIEW-CHECKLIST.md`	布局前验证清单
`reference/ERC-VIOLATIONS-GUIDE.md`	ERC错误修复指南

Next Steps

后续步骤

After schematic is complete:

Generate netlist
Run
```
/eda-layout
```
to begin PCB layout
Update
```
design-constraints.json
```
stage to "pcb"

原理图完成后：

生成网表
运行
```
/eda-layout
```
开始PCB布局
将
```
design-constraints.json
```
中的阶段更新为"pcb"