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DMA attacks exploit the ability of PCIe devices to directly access
system memory without CPU involvement. An attacker can:
- Read arbitrary physical memory
- Write to physical memory
- Bypass software-based protections
- Remain invisible to OS-level detectionDMA attacks exploit the ability of PCIe devices to directly access
system memory without CPU involvement. An attacker can:
- Read arbitrary physical memory
- Write to physical memory
- Bypass software-based protections
- Remain invisible to OS-level detection- FPGA development board (Xilinx/Altera)
- PCIe interface capability
- Sufficient logic resources
- Development environment- FPGA development board (Xilinx/Altera)
- PCIe interface capability
- Sufficient logic resources
- Development environment- Screamer PCIe (Xilinx Artix-7)
- PCIe Squirrel
- AC701 (Xilinx Artix-7)
- SP605 (Xilinx Spartan-6)
- Custom FPGA boards- Screamer PCIe (Xilinx Artix-7)
- PCIe Squirrel
- AC701 (Xilinx Artix-7)
- SP605 (Xilinx Spartan-6)
- Custom FPGA boardsundefinedundefinedundefinedundefined- Vivado (Xilinx)
- Quartus (Intel/Altera)
- Open-source toolchains- Vivado (Xilinx)
- Quartus (Intel/Altera)
- Open-source toolchains- TLP packet generation
- Configuration space emulation
- MSI/MSI-X interrupt handling
- DMA read/write implementation- TLP packet generation
- Configuration space emulation
- MSI/MSI-X interrupt handling
- DMA read/write implementation- Device ID spoofing
- Vendor ID masquerading
- Serial number randomization
- Capability structure emulation- Device ID spoofing
- Vendor ID masquerading
- Serial number randomization
- Capability structure emulation- Network adapters (Intel I210/I226)
- Storage controllers
- USB controllers
- Sound cards- Network adapters (Intel I210/I226)
- Storage controllers
- USB controllers
- Sound cards1. Correct PCI configuration space
2. Proper capability structures
3. BAR (Base Address Register) setup
4. Interrupt handling1. Correct PCI configuration space
2. Proper capability structures
3. BAR (Base Address Register) setup
4. Interrupt handling- Emulate Intel I210 NIC
- Proper device/vendor ID
- PHY register emulation
- Minimal functionality for detection evasion- Emulate Intel I210 NIC
- Proper device/vendor ID
- PHY register emulation
- Minimal functionality for detection evasion// Typical pcileech API usage
HANDLE hDevice;
BYTE buffer[0x1000];
// Read physical memory
pcileech_read_phys(hDevice, physAddr, buffer, sizeof(buffer));// Typical pcileech API usage
HANDLE hDevice;
BYTE buffer[0x1000];
// Read physical memory
pcileech_read_phys(hDevice, physAddr, buffer, sizeof(buffer));// Walk page tables to translate VA to PA
PHYSICAL_ADDRESS TranslateVA(UINT64 cr3, UINT64 virtualAddr) {
// PML4 -> PDPT -> PD -> PT -> Physical
UINT64 pml4e = ReadPhys(cr3 + PML4_INDEX(virtualAddr) * 8);
UINT64 pdpte = ReadPhys(PFN(pml4e) + PDPT_INDEX(virtualAddr) * 8);
UINT64 pde = ReadPhys(PFN(pdpte) + PD_INDEX(virtualAddr) * 8);
UINT64 pte = ReadPhys(PFN(pde) + PT_INDEX(virtualAddr) * 8);
return PFN(pte) + PAGE_OFFSET(virtualAddr);
}// Walk page tables to translate VA to PA
PHYSICAL_ADDRESS TranslateVA(UINT64 cr3, UINT64 virtualAddr) {
// PML4 -> PDPT -> PD -> PT -> Physical
UINT64 pml4e = ReadPhys(cr3 + PML4_INDEX(virtualAddr) * 8);
UINT64 pdpte = ReadPhys(PFN(pml4e) + PDPT_INDEX(virtualAddr) * 8);
UINT64 pde = ReadPhys(PFN(pdpte) + PD_INDEX(virtualAddr) * 8);
UINT64 pte = ReadPhys(PFN(pde) + PT_INDEX(virtualAddr) * 8);
return PFN(pte) + PAGE_OFFSET(virtualAddr);
}- Scan physical memory for valid CR3 values
- Look for kernel structures
- Use signature scanning
- Validate page table entries- Scan physical memory for valid CR3 values
- Look for kernel structures
- Use signature scanning
- Validate page table entries- CE server for DMA access
- Process memory reading via DMA
- Remote debugging capability- CE server for DMA access
- Process memory reading via DMA
- Remote debugging capability- Structure reconstruction
- Live memory viewing
- Pointer scanning- Structure reconstruction
- Live memory viewing
- Pointer scanning- DMA libraries (DMALib)
- Minimal VM libraries
- Game-specific cheats- DMA libraries (DMALib)
- Minimal VM libraries
- Game-specific cheats1. No process attachment
2. No suspicious API calls
3. No kernel driver needed
4. No code injection
5. Operates below OS level1. No process attachment
2. No suspicious API calls
3. No kernel driver needed
4. No code injection
5. Operates below OS level- Read-only for some implementations
- Timing-based detection possible
- Hardware fingerprinting
- Memory encryption (on newer systems)- Read-only for some implementations
- Timing-based detection possible
- Hardware fingerprinting
- Memory encryption (on newer systems)- PCIe device enumeration
- IOMMU/VT-d monitoring
- DMA buffer analysis
- Performance counter anomalies- PCIe device enumeration
- IOMMU/VT-d monitoring
- DMA buffer analysis
- Performance counter anomalies- pcileech-wifi: Wireless card emulation
- Remote memory access
- Extended range operation- pcileech-wifi: Wireless card emulation
- Remote memory access
- Extended range operation- Ring -2 execution
- Highest privilege level
- Extremely stealthy
- Complex implementation- Ring -2 execution
- Highest privilege level
- Extremely stealthy
- Complex implementation- Virtual Management Device
- Hide behind Intel VMD
- Complex detection evasion- Virtual Management Device
- Hide behind Intel VMD
- Complex detection evasion/firmware
├── src/
│ ├── pcie_core.v # PCIe core
│ ├── tlp_handler.v # TLP processing
│ ├── dma_engine.v # DMA implementation
│ └── config_space.v # Config emulation
├── constraints/
│ └── board.xdc # Pin constraints
└── scripts/
└── build.tcl # Build script/firmware
├── src/
│ ├── pcie_core.v # PCIe core
│ ├── tlp_handler.v # TLP processing
│ ├── dma_engine.v # DMA implementation
│ └── config_space.v # Config emulation
├── constraints/
│ └── board.xdc # Pin constraints
└── scripts/
└── build.tcl # Build script// TLP packet handling
module tlp_handler (
input wire clk,
input wire [127:0] rx_data,
output reg [127:0] tx_data,
// DMA interface
output reg [63:0] dma_addr,
output reg [31:0] dma_data,
output reg dma_read,
output reg dma_write
);// TLP packet handling
module tlp_handler (
input wire clk,
input wire [127:0] rx_data,
output reg [127:0] tx_data,
// DMA interface
output reg [63:0] dma_addr,
output reg [31:0] dma_data,
output reg dma_read,
output reg dma_write
);- Security research only
- Authorized testing environments
- Responsible disclosure
- Legal compliance- Security research only
- Authorized testing environments
- Responsible disclosure
- Legal compliance- Physical hardware access required
- Potential system instability
- Detection by advanced anti-cheat
- Legal implications- Physical hardware access required
- Potential system instability
- Detection by advanced anti-cheat
- Legal implicationshttps://raw.githubusercontent.com/gmh5225/awesome-game-security/refs/heads/main/README.mdhttps://raw.githubusercontent.com/gmh5225/awesome-game-security/refs/heads/main/README.md