wire-lang

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Original

English

🇨🇳

Translation

Chinese

Wire Lang Authoring Skill

Wire Lang 创作技能

Use this skill to help people author Wire Lang source. Wire Lang is a textual language for describing electronic schematics and rendering them as readable SVG diagrams.

本技能用于帮助用户编写Wire Lang源码。Wire Lang是一种文本语言，用于描述电子原理图并将其渲染为易读的SVG图表。

First Move For Authoring

创作第一步

Identify the circuit the user wants to describe.
Choose component instances and stable instance IDs.
Connect terminals through named nets or
```
connect
```
statements.
Add title, description, annotations, and render hints only when useful.
Check the source with
```
wire check
```
when the CLI is available.

Read the focused reference files as needed:

```
references/concept-map.md
```
for the authoring concept graph.
```
references/source-format.md
```
for syntax and statement shapes.
```
references/component-library.md
```
for standard components, terminals, and properties.
```
references/style-guide.md
```
for source-writing conventions.
```
references/examples.md
```
for good and bad examples.
```
references/boundaries.md
```
when a user asks for simulation, PCB layout, breadboard layout, BOMs, custom symbols, or browser/editor integrations.

明确用户想要描述的电路。
选择组件实例及稳定的实例ID。
通过命名网络或
```
connect
```
语句连接端子。
仅在必要时添加标题、描述、注释和渲染提示。
当CLI可用时，使用
```
wire check
```
检查源码。

按需阅读以下针对性参考文件：

```
references/concept-map.md
```
：创作概念图。
```
references/source-format.md
```
：语法与语句结构。
```
references/component-library.md
```
：标准组件、端子及属性。
```
references/style-guide.md
```
：源码编写规范。
```
references/examples.md
```
：正反示例。
```
references/boundaries.md
```
：当用户询问仿真、PCB布局、面包板布局、物料清单（BOM）、自定义符号或浏览器/编辑器集成时查阅。

Validate And Render

验证与渲染

Use the

wire

CLI instead of hand-validating whenever the user's environment can run it:

bash

npm i -D wire-lang
npx wire check path/to/circuit.wire
npx wire render path/to/circuit.wire --out path/to/circuit.svg
npx wire watch path/to/circuit.wire --out path/to/circuit.svg

For a one-off run without adding a package to the project, invoke the

wire

binary from the

wire-lang

package:

bash

npx -p wire-lang wire check path/to/circuit.wire
npx -p wire-lang wire render path/to/circuit.wire --out path/to/circuit.svg

Use
```
wire check
```
as the real implementation of checking the source against MVP syntax and the component library.
Use
```
wire render <file>.wire --out <file>.svg
```
as the canonical author-to-SVG artifact step.
Use
```
wire watch <file>.wire --out <file>.svg
```
while iterating.
Add
```
--json
```
to
```
wire check
```
,
```
wire render
```
, or
```
wire watch
```
when machine-readable diagnostics are useful.
Markdown does not auto-render fenced
```
wire
```
blocks in the MVP. The intended documentation workflow is: author
```
.wire
```
-> run
```
wire render
```
-> link or embed the generated
```
.svg
```
.
Do not claim that source was checked or rendered unless the command actually ran. If the CLI is unavailable, say the source is not tool-validated and give the exact command to run.

只要用户环境可运行

wire

CLI，就使用它而非手动验证：

bash

npm i -D wire-lang
npx wire check path/to/circuit.wire
npx wire render path/to/circuit.wire --out path/to/circuit.svg
npx wire watch path/to/circuit.wire --out path/to/circuit.svg

若不想向项目添加依赖包，可直接从

wire-lang

包调用

wire

二进制文件进行一次性运行：

bash

npx -p wire-lang wire check path/to/circuit.wire
npx -p wire-lang wire render path/to/circuit.wire --out path/to/circuit.svg

使用
```
wire check
```
作为验证源码是否符合MVP语法及组件库的标准方式。
使用
```
wire render <file>.wire --out <file>.svg
```
作为从源码生成SVG文件的标准步骤。
迭代开发时使用
```
wire watch <file>.wire --out <file>.svg
```
。
当需要机器可读的诊断信息时，为
```
wire check
```
、
```
wire render
```
或
```
wire watch
```
添加
```
--json
```
参数。
MVP版本中，Markdown不会自动渲染 fenced
```
wire
```
代码块。标准文档流程为：编写
```
.wire
```
文件 -> 运行
```
wire render
```
-> 链接或嵌入生成的
```
.svg
```
文件。
除非实际运行了命令，否则不要声称源码已被检查或渲染。若CLI不可用，需说明源码未经过工具验证，并给出具体的运行命令。

Authoring Rules

创作规则

Start every MVP source with
```
schematic
```
.
Use
```
.wire
```
source to describe logical schematics, not breadboards, PCB layouts, physical routing, or simulations.
Declare component instances with
```
component ID Type ...
```
.
Use canonical component names and terminal names from the standard library.
Use named nets for important or reused electrical nodes such as
```
VCC
```
,
```
5V
```
,
```
3V3
```
,
```
GND
```
,
```
SDA
```
, or
```
SCL
```
.
Use
```
connect
```
for simple anonymous connections.
Treat power nets as normal nets; they do not create hidden connections.
Use
```
annotation
```
for visible explanatory text. Use
```
//
```
only for source comments.
Use render hints for layout guidance, not electrical meaning.
Do not invent unsupported syntax. If Wire Lang cannot express the user's request in the MVP, say so and offer the closest valid source.

所有MVP版本的源码都必须以
```
schematic
```
开头。
使用
```
.wire
```
源码描述逻辑原理图，而非面包板、PCB布局、物理布线或仿真内容。
使用
```
component ID Type ...
```
声明组件实例。
使用标准库中的规范组件名称和端子名称。
为重要或复用的电气节点使用命名网络，如
```
VCC
```
、
```
5V
```
、
```
3V3
```
、
```
GND
```
、
```
SDA
```
或
```
SCL
```
。
使用
```
connect
```
进行简单的匿名连接。
将电源网络视为普通网络；它们不会创建隐式连接。
使用
```
annotation
```
添加可见的解释性文本。仅使用
```
//
```
作为源码注释。
使用渲染提示指导布局，而非承载电气含义。
不要自创不支持的语法。若Wire Lang的MVP版本无法表达用户的需求，需明确说明并提供最接近的有效源码。

Default Output

默认输出

When asked to create Wire Lang source, return a complete

.wire

block:

wire

schematic
  title "..."
  description "..."

  component ...

  net ...
  connect ...

After the block, include a short note only for important assumptions, such as component choices or unsupported requested behavior.

When the user asks for an image or SVG artifact, include the

wire render

command to produce it. If you ran the command successfully, include the output path; otherwise, state that rendering has not been tool-verified.

当被要求创建Wire Lang源码时，返回完整的

.wire

代码块：

wire

schematic
  title "..."
  description "..."

  component ...

  net ...
  connect ...

代码块之后，仅在存在重要假设时添加简短说明，例如组件选择或不支持的请求行为。

当用户要求提供图片或SVG文件时，需包含生成该文件的

wire render

命令。若已成功运行命令，需注明输出路径；否则，说明渲染未经过工具验证。

Common Corrections

常见修正

"Draw a wire from X to Y" usually means create a
```
connect
```
statement or named
```
net
```
; do not encode visual paths.
"Show this note in the diagram" means use
```
annotation
```
, not
```
//
```
.
"Ground everything" still requires explicit
```
GND
```
net connections.
"Make this vertical" is a render hint, not a component property.
"Arduino board" is outside the MVP standard library; model it as a local module-style component if needed.
"Chip with numbered pins" is the
```
IC
```
type:
```
pins=[1:VCC@left, 2:GND@left, 3:OUT@right]
```
. Connect pins by name.
"Leave this pin unused / N.C." is a
```
no-connect TERMINAL
```
statement, not a floating net.
"Mark the 3V3 rail" can use a
```
PowerFlag name=3V3
```
; it is a visual flag, not a hidden global net.
Crossings without a junction are left simply overlapping by default; "draw a hop where lines cross" is
```
render crossings=hop
```
.

“在X和Y之间画一根线”通常意味着创建
```
connect
```
语句或命名
```
net
```
；不要编码视觉路径。
“在图表中显示此注释”意味着使用
```
annotation
```
，而非
```
//
```
。
“将所有部件接地”仍需显式连接
```
GND
```
网络。
“使其垂直”是渲染提示，而非组件属性。
“Arduino开发板”不在MVP标准库中；必要时可将其建模为本地模块式组件。
“带引脚编号的芯片”属于
```
IC
```
类型：
```
pins=[1:VCC@left, 2:GND@left,3:OUT@right]
```
。通过引脚名称进行连接。
“此引脚留空/不连接”需使用
```
no-connect TERMINAL
```
语句，而非悬空网络。
“标记3V3电源轨”可使用
```
PowerFlag name=3V3
```
；这是一个视觉标记，而非隐式全局网络。
默认情况下，无交叉点的线路仅简单重叠；“在线路交叉处绘制跳点”需使用
```
render crossings=hop
```
。

Keep This Skill Current

保持技能更新

When the Wire Lang syntax, examples, standard component library, or MVP authoring rules change, update this skill and the focused reference files.

Before finishing an authoring response, check:

The source starts with
```
schematic
```
.
Component types and terminal names exist in the standard library or in a local component definition.
Power nets are explicitly connected.
Visible explanatory text uses
```
annotation
```
, not
```
//
```
.
Render hints do not carry electrical meaning.
Unsupported requests are called out with the closest valid MVP expression.

当Wire Lang的语法、示例、标准组件库或MVP创作规则发生变化时，需更新本技能及针对性参考文件。

完成创作响应前，请检查：

源码以
```
schematic
```
开头。
组件类型和端子名称存在于标准库或本地组件定义中。
电源网络已显式连接。
可见的解释性文本使用
```
annotation
```
，而非
```
//
```
。
渲染提示未承载电气含义。
已明确指出不支持的请求，并提供最接近的MVP有效表达。