find-high-speed-nets

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Find High-Speed Nets

识别高速网络

When this skill is invoked with a KiCad PCB file, perform a comprehensive analysis to identify which nets carry high-speed signals and recommend appropriate signal integrity measures.

当调用该功能并传入KiCad PCB文件时，将执行全面分析以识别哪些网络承载高速信号，并推荐合适的信号完整性措施。

Step 1: Load and Extract Components

步骤1：加载并提取元件

python

from kicad_parser import parse_kicad_pcb
pcb = parse_kicad_pcb('path/to/file.kicad_pcb')

python

from kicad_parser import parse_kicad_pcb
pcb = parse_kicad_pcb('path/to/file.kicad_pcb')

Basic stats

print(f'Total nets: {len(pcb.nets)}') print(f'Total footprints: {len(pcb.footprints)}')


Also run `list_nets.py` to get differential pairs and power nets (these inform the analysis):

```bash
python3 list_nets.py path/to/file.kicad_pcb --diff-pairs --power

Note: Differential pairs are handled separately by

route_diff.py

, which adds its own GND return vias automatically. This analysis focuses on single-ended signal vias from

route.py

print(f'Total nets: {len(pcb.nets)}') print(f'Total footprints: {len(pcb.footprints)}')


同时运行`list_nets.py`以获取差分对和电源网络（这些信息会用于分析）：

```bash
python3 list_nets.py path/to/file.kicad_pcb --diff-pairs --power

注意：差分对由

route_diff.py

单独处理，它会自动添加对应的GND过孔。本次分析聚焦于

route.py

处理的单端信号过孔。

Step 2: Pre-Classify Nets by Name Patterns

步骤2：通过名称模式预分类网络

Scan all net names (case-insensitive) to get an initial speed estimate before datasheet lookup:

python

speed_tiers = {
    'ultra_high': {  # >1 GHz
        'patterns': ['DDR3', 'DDR4', 'DDR5', 'LPDDR', 'PCIE', 'SATA',
                     'USB3', 'SGMII', 'XGMII', 'TMDS', '10G'],
        'typical_freq_mhz': 1600,
        'typical_rise_ns': 0.3,
    },
    'high': {  # 100 MHz - 1 GHz
        'patterns': ['DDR', 'DQ', 'DQS', 'DQM', 'RGMII', 'RMII',
                     'QSPI', 'QIO', 'SDIO', 'LVDS', 'HDMI',
                     'USB', 'ETH', 'ULPI', 'EMMC'],
        'typical_freq_mhz': 200,
        'typical_rise_ns': 1.0,
    },
    'medium': {  # 10 - 100 MHz
        'patterns': ['SPI', 'SCK', 'SCLK', 'MOSI', 'MISO',
                     'CLK', 'MCLK', 'BCLK', 'JTAG', 'TCK',
                     'TDI', 'TDO', 'TMS', 'SWDIO', 'SWCLK',
                     'CAN', 'SDMMC'],
        'typical_freq_mhz': 50,
        'typical_rise_ns': 3.0,
    },
    'low': {  # <10 MHz
        'patterns': ['I2C', 'SCL', 'SDA', 'UART', 'TX', 'RX',
                     'GPIO', 'LED', 'BTN', 'SW_', 'ADC', 'DAC',
                     'PWM', 'RST', 'RESET', 'EN', 'ENABLE',
                     'IRQ', 'INT'],
        'typical_freq_mhz': 1,
        'typical_rise_ns': 10.0,
    },
}

扫描所有网络名称（不区分大小写），在查找Datasheet前先进行初步的速度估算：

python

speed_tiers = {
    'ultra_high': {  # >1 GHz
        'patterns': ['DDR3', 'DDR4', 'DDR5', 'LPDDR', 'PCIE', 'SATA',
                     'USB3', 'SGMII', 'XGMII', 'TMDS', '10G'],
        'typical_freq_mhz': 1600,
        'typical_rise_ns': 0.3,
    },
    'high': {  # 100 MHz - 1 GHz
        'patterns': ['DDR', 'DQ', 'DQS', 'DQM', 'RGMII', 'RMII',
                     'QSPI', 'QIO', 'SDIO', 'LVDS', 'HDMI',
                     'USB', 'ETH', 'ULPI', 'EMMC'],
        'typical_freq_mhz': 200,
        'typical_rise_ns': 1.0,
    },
    'medium': {  # 10 - 100 MHz
        'patterns': ['SPI', 'SCK', 'SCLK', 'MOSI', 'MISO',
                     'CLK', 'MCLK', 'BCLK', 'JTAG', 'TCK',
                     'TDI', 'TDO', 'TMS', 'SWDIO', 'SWCLK',
                     'CAN', 'SDMMC'],
        'typical_freq_mhz': 50,
        'typical_rise_ns': 3.0,
    },
    'low': {  # <10 MHz
        'patterns': ['I2C', 'SCL', 'SDA', 'UART', 'TX', 'RX',
                     'GPIO', 'LED', 'BTN', 'SW_', 'ADC', 'DAC',
                     'PWM', 'RST', 'RESET', 'EN', 'ENABLE',
                     'IRQ', 'INT'],
        'typical_freq_mhz': 1,
        'typical_rise_ns': 10.0,
    },
}

Build initial classification

net_speed = {} # {net_name: (tier, interface_guess, freq_mhz)} for net in pcb.nets.values(): if not net.name or net.name == '': continue name_upper = net.name.upper() for tier, info in speed_tiers.items(): if any(pat in name_upper for pat in info['patterns']): net_speed[net.name] = (tier, 'name_match', info['typical_freq_mhz']) break


Report the initial classification to the user: how many nets in each tier, which patterns matched.


向用户报告初步分类结果：每个速度等级的网络数量，以及匹配的模式。

Step 3: Pre-Classify Components by Footprint and Value

步骤3：通过封装和元件值预分类元件

Check footprint names and component values for high-speed indicators:

python

hs_component_keywords = {
    'FPGA':  ('ultra_high', 'Programmable logic - likely LVDS/DDR/SerDes'),
    'CPLD':  ('high',       'Programmable logic - check I/O speed'),
    'DDR':   ('ultra_high', 'DDR memory'),
    'SDRAM': ('high',       'SDRAM - check generation (DDR2/3/4)'),
    'LPDDR': ('ultra_high', 'Low-power DDR memory'),
    'USB':   ('high',       'USB interface - check version (1.1/2.0/3.x)'),
    'ETH':   ('high',       'Ethernet - check speed (10/100/1000)'),
    'PHY':   ('high',       'PHY transceiver - check interface type'),
    'SERDES':('ultra_high', 'Serializer/deserializer'),
    'XCVR':  ('ultra_high', 'Transceiver - multi-GHz serial'),
    'HDMI':  ('ultra_high', 'HDMI - TMDS lanes'),
}

high_speed_components = []  # [(ref, footprint, tier, notes)]
for ref, fp in pcb.footprints.items():
    name_upper = fp.footprint_name.upper()
    for kw, (tier, notes) in hs_component_keywords.items():
        if kw in name_upper:
            high_speed_components.append((ref, fp.footprint_name, tier, notes))
            break

检查封装名称和元件值，寻找高速信号的标识：

python

hs_component_keywords = {
    'FPGA':  ('ultra_high', 'Programmable logic - likely LVDS/DDR/SerDes'),
    'CPLD':  ('high',       'Programmable logic - check I/O speed'),
    'DDR':   ('ultra_high', 'DDR memory'),
    'SDRAM': ('high',       'SDRAM - check generation (DDR2/3/4)'),
    'LPDDR': ('ultra_high', 'Low-power DDR memory'),
    'USB':   ('high',       'USB interface - check version (1.1/2.0/3.x)'),
    'ETH':   ('high',       'Ethernet - check speed (10/100/1000)'),
    'PHY':   ('high',       'PHY transceiver - check interface type'),
    'SERDES':('ultra_high', 'Serializer/deserializer'),
    'XCVR':  ('ultra_high', 'Transceiver - multi-GHz serial'),
    'HDMI':  ('ultra_high', 'HDMI - TMDS lanes'),
}

high_speed_components = []  # [(ref, footprint, tier, notes)]
for ref, fp in pcb.footprints.items():
    name_upper = fp.footprint_name.upper()
    for kw, (tier, notes) in hs_component_keywords.items():
        if kw in name_upper:
            high_speed_components.append((ref, fp.footprint_name, tier, notes))
            break

Also flag ICs with high pin count (>40 pins) as likely having fast interfaces

for ref, fp in pcb.footprints.items(): if ref.upper().startswith('U') and len(fp.pads) > 40: if ref not in [c[0] for c in high_speed_components]: high_speed_components.append((ref, fp.footprint_name, 'unknown', f'{len(fp.pads)}-pin IC - needs datasheet lookup'))


Report components found and which need AI analysis.


报告找到的元件以及哪些需要AI分析。

Step 4: AI Datasheet Lookup

步骤4：AI Datasheet 查找

For each IC (U*), non-trivial connector, and any component flagged in Step 3, use WebSearch to find datasheet information about signal speeds.

对于每个IC（U*标识）、非普通连接器，以及步骤3中标记的任何元件，使用WebSearch查找有关信号速度的Datasheet信息。

4a. Search for Interface Speeds

4a. 搜索接口速度

WebSearch: "<part_value> <footprint_hint> datasheet maximum clock frequency"

Examples:

"MCF5213 ColdFire datasheet bus clock speed"

- Find MCU bus frequency

"XCR3256 CPLD datasheet I/O toggle rate"

- Find CPLD max speed

"KSZ9031 Ethernet PHY datasheet RGMII clock"

- Find PHY interface speed

"W25Q128 QSPI flash datasheet SPI clock frequency"

- Find flash max SPI clock

```
"FT2232H USB datasheet interface speed"
```
- Find USB version and speed

"IS42S16160 SDRAM datasheet CAS latency clock"

- Find SDRAM clock speed

"STM32F407 datasheet peripheral clock speeds"

- Find MCU interface speeds

WebSearch: "<part_value> <footprint_hint> datasheet maximum clock frequency"

示例：

"MCF5213 ColdFire datasheet bus clock speed"

- 查找MCU总线频率

"XCR3256 CPLD datasheet I/O toggle rate"

- 查找CPLD最大速度

"KSZ9031 Ethernet PHY datasheet RGMII clock"

- 查找PHY接口速度

"W25Q128 QSPI flash datasheet SPI clock frequency"

- 查找Flash最大SPI时钟

```
"FT2232H USB datasheet interface speed"
```
- 查找USB版本和速度

"IS42S16160 SDRAM datasheet CAS latency clock"

- 查找SDRAM时钟速度

"STM32F407 datasheet peripheral clock speeds"

- 查找MCU外设接口速度

4b. Extract Speed Information

4b. 提取速度信息

From each datasheet result, extract:

Field	What to Look For
Interface type	SPI, I2C, UART, USB 2.0 HS, DDR3-1600, RGMII, etc.
Max clock/data rate	Bus clock in MHz/GHz, data rate in MT/s or Gbps
Output rise time	tr/tf in ns or ps (often in "Switching Characteristics" table)
I/O standards	LVCMOS, LVTTL, LVDS, HSTL, SSTL (for FPGAs)

从每个Datasheet结果中，提取以下信息：

字段	查找内容
接口类型	SPI、I2C、UART、USB 2.0 HS、DDR3-1600、RGMII等
最大时钟/数据速率	总线时钟（MHz/GHz）、数据速率（MT/s或Gbps）
输出上升时间	tr/tf（纳秒或皮秒，通常在“开关特性”表格中）
I/O标准	LVCMOS、LVTTL、LVDS、HSTL、SSTL（针对FPGA）

4c. Map to Specific Pins and Nets

4c. 映射到特定引脚和网络

For each interface found, identify which pins carry the fast signals:

python

undefined

对于找到的每个接口，识别哪些引脚承载高速信号：

python

undefined

Map IC interface pins to nets

for ref, fp in pcb.footprints.items(): for pad in fp.pads: if pad.pinfunction: func_upper = pad.pinfunction.upper() # Check if this pin is part of a high-speed interface # e.g., pinfunction="SPI_CLK" on an MCU → that net is SPI speed


Record per-component findings:
- Component ref and value
- Each interface found: protocol, max frequency, rise time (if available)
- Which net names are associated with each interface


记录每个元件的查找结果：
- 元件编号和型号
- 找到的每个接口：协议、最大频率、上升时间（如果有）
- 每个接口关联的网络名称

4d. Update Net Classifications

4d. 更新网络分类

Upgrade net classifications based on datasheet findings. A datasheet-confirmed speed always overrides the name-pattern estimate from Step 2.

根据Datasheet的查找结果升级网络分类。Datasheet确认的速度始终覆盖步骤2中通过名称模式得到的估算值。

Step 5: Trace High-Speed Signals Through Series Passives

步骤5：追踪高速信号经过的串联无源元件

High-speed signals often pass through series components (termination resistors, AC coupling caps, ferrite beads). The nets on both sides carry the same speed signal.

python

undefined

高速信号通常会经过串联元件（终端电阻、AC耦合电容、磁珠）。元件两侧的网络承载相同速度的信号。

python

undefined

Build map of 2-pad series passives

series_passives = {} # {ref: (net_a, net_b)} for ref, fp in pcb.footprints.items(): ref_upper = ref.upper() is_passive = any(ref_upper.startswith(p) and (len(ref_upper) <= 1 or ref_upper[len(p):len(p)+1].isdigit()) for p in ['R', 'C', 'L', 'FB']) if is_passive and len(fp.pads) == 2: net_a = fp.pads[0].net_name net_b = fp.pads[1].net_name if net_a and net_b and net_a != net_b: series_passives[ref] = (net_a, net_b)

BFS: propagate speed classification through series passives

If net_a is classified high-speed, net_b inherits the same classification

from collections import deque

def propagate_speeds(net_speed, series_passives): # Build adjacency: net → [connected nets via passives] adjacency = {} for ref, (net_a, net_b) in series_passives.items(): adjacency.setdefault(net_a, []).append(net_b) adjacency.setdefault(net_b, []).append(net_a)

# BFS from each classified net
propagated = {}
for net_name, (tier, interface, freq) in list(net_speed.items()):
    queue = deque([net_name])
    visited = {net_name}
    while queue:
        current = queue.popleft()
        for neighbor in adjacency.get(current, []):
            if neighbor not in visited and neighbor not in net_speed:
                propagated[neighbor] = (tier, f'{interface} via series passive', freq)
                visited.add(neighbor)
                queue.append(neighbor)

net_speed.update(propagated)
return propagated  # return newly classified nets for reporting


Report which nets were added by propagation (e.g., "Net-R1-Pad2 classified as high-speed
via series resistor R1 from SPI_CLK").

from collections import deque

# BFS from each classified net
propagated = {}
for net_name, (tier, interface, freq) in list(net_speed.items()):
    queue = deque([net_name])
    visited = {net_name}
    while queue:
        current = queue.popleft()
        for neighbor in adjacency.get(current, []):
            if neighbor not in visited and neighbor not in net_speed:
                propagated[neighbor] = (tier, f'{interface} via series passive', freq)
                visited.add(neighbor)
                queue.append(neighbor)

net_speed.update(propagated)
return propagated  # return newly classified nets for reporting


报告通过传播新增的网络分类（例如：“Net-R1-Pad2 通过串联电阻R1从SPI_CLK继承高速分类”）。

Step 6: Generate Report

步骤6：生成报告

Per-Interface Groups

按接口分组

Group nets by interface and source/destination components:

undefined

按接口和源/目标元件对网络进行分组：

undefined

High-Speed Net Analysis for board.kicad_pcb

针对board.kicad_pcb的高速网络分析

Interface Groups

接口分组

SPI bus: U1 (STM32F407) <-> U3 (W25Q128)

/SPI_CLK: 50 MHz (datasheet-confirmed)
/SPI_MOSI: 50 MHz (same bus)
/SPI_MISO: 50 MHz (same bus)
/SPI_CS: 50 MHz (same bus)
Speed class: Medium

DDR3 memory: U1 <-> U5 (MT41K256)

/DDR_DQ0..DQ15: 800 MHz (DDR3-1600)
/DDR_DQS0, DQS1: 800 MHz
/DDR_CLK: 800 MHz
/DDR_A0..A14: 800 MHz
Speed class: Ultra-high

undefined

SPI总线：U1（STM32F407）<-> U3（W25Q128）

/SPI_CLK：50 MHz（Datasheet确认）
/SPI_MOSI：50 MHz（同总线）
/SPI_MISO：50 MHz（同总线）
/SPI_CS：50 MHz（同总线）
速度等级：中速

DDR3内存：U1 <-> U5（MT41K256）

/DDR_DQ0..DQ15：800 MHz（DDR3-1600）
/DDR_DQS0、DQS1：800 MHz
/DDR_CLK：800 MHz
/DDR_A0..A14：800 MHz
速度等级：超高速

undefined

Speed Summary Table

速度汇总表

| Net Name | Interface | Component | Max Freq | Rise Time | Speed Class |
|----------|-----------|-----------|----------|-----------|-------------|
| /DDR_DQ0 | DDR3 | U1<->U5 | 800 MHz | ~0.3 ns | Ultra-high |
| /SPI_CLK | SPI | U1<->U3 | 50 MHz | ~3 ns | Medium |
| /I2C_SCL | I2C | U1<->U2 | 400 kHz | ~100 ns | Low |

| 网络名称 | 接口类型 | 元件 | 最大频率 | 上升时间 | 速度等级 |
|----------|-----------|-----------|----------|-----------|-------------|
| /DDR_DQ0 | DDR3 | U1<->U5 | 800 MHz | ~0.3 ns | 超高速 |
| /SPI_CLK | SPI | U1<->U3 | 50 MHz | ~3 ns | 中速 |
| /I2C_SCL | I2C | U1<->U2 | 400 kHz | ~100 ns | 低速 |

GND Return Via Recommendation

接地过孔推荐

Based on the highest speed class found on the board:

Speed Class	Frequency	Recommended `--gnd-via-distance`	Rationale
Ultra-high	>1 GHz	2.0 mm	Return path critical; lambda/20 ~ 7 mm at 1 GHz in FR4
High	100 MHz - 1 GHz	3.0 mm	Good return path, moderate density
Medium	10 - 100 MHz	5.0 mm	Return current less localized
Low	<10 MHz	Skip	Plane provides adequate return path
Minimum physical	any	3 x (via_size + clearance)	Vias cannot physically fit closer

For this board, the tightest interface is [interface] at [freq], so use:

--add-gnd-vias --gnd-via-distance [recommended_value]

Note: Differential pairs (detected by

/plan-pcb-routing

list_nets.py --diff-pairs

) are routed with

route_diff.py

, which adds its own GND return vias automatically. The

--gnd-via-distance

recommendation here applies to single-ended signal vias only.

根据板上找到的最高速度等级：

速度等级	频率范围	推荐的 `--gnd-via-distance`	理由
超高速	>1 GHz	2.0 mm	返回路径至关重要；FR4板材中1 GHz信号的λ/20约为7 mm
高速	100 MHz - 1 GHz	3.0 mm	良好的返回路径，兼顾板密度
中速	10 - 100 MHz	5.0 mm	返回电流的局部性较弱
低速	<10 MHz	跳过	接地平面可提供足够的返回路径
最小物理间距	任意	3 x (过孔尺寸 + 安全间距)	过孔无法在更近的距离下物理放置

对于该电路板，最严苛的接口是**[接口名称]，频率为[频率]**，因此使用：

--add-gnd-vias --gnd-via-distance [推荐值]

注意：差分对（由

/plan-pcb-routing

或

list_nets.py --diff-pairs

检测）由

route_diff.py

布线，它会自动添加对应的GND过孔。此处的

--gnd-via-distance

推荐仅适用于

route.py

处理的单端信号过孔。

Impedance Notes (if applicable)

阻抗说明（如适用）

If high-speed interfaces are detected, note relevant impedance targets:

Interface	Typical Impedance	Notes
DDR3/4	40 ohm SE	SSTL, check memory controller spec
USB 2.0 HS	90 ohm diff	Routed as diff pair
USB 3.x	85 ohm diff	Routed as diff pair
Gigabit Ethernet	100 ohm diff	Routed as diff pair
LVDS	100 ohm diff	Routed as diff pair
PCIe	85 ohm diff	Routed as diff pair
SPI/I2C/UART	50 ohm SE (typical)	Usually not impedance-controlled

如果检测到高速接口，记录相关的阻抗目标：

接口类型	典型阻抗	说明
DDR3/4	40 ohm 单端	SSTL标准，请查阅内存控制器规格
USB 2.0 HS	90 ohm 差分	按差分对布线
USB 3.x	85 ohm 差分	按差分对布线
千兆以太网	100 ohm 差分	按差分对布线
LVDS	100 ohm 差分	按差分对布线
PCIe	85 ohm 差分	按差分对布线
SPI/I2C/UART	50 ohm 单端（典型值）	通常无需阻抗控制

Important Notes

重要注意事项

Datasheet results override name-pattern guesses - A net named "CLK" could be 1 MHz or 1 GHz; the datasheet determines the actual speed
Check all ICs, not just the obvious ones - A "simple" MCU may have USB HS, SDIO, or QSPI peripherals running at hundreds of MHz
Series passives propagate speed - The net on the other side of a termination resistor or AC coupling cap carries the same speed signal
Use the tightest distance - If the board has both DDR3 (ultra-high) and I2C (low), the GND return via distance should be set for the DDR3 signals (2.0 mm)
Diff pairs are separate -
```
route_diff.py
```
handles GND return vias for differential pairs independently; this analysis is for single-ended vias from
```
route.py
```
When in doubt, include GND return vias - They cost only board space; omitting them on a board that needs them causes signal integrity and EMI problems

Datasheet结果优先于名称模式猜测 - 名为“CLK”的网络可能是1 MHz或1 GHz；Datasheet决定实际速度
检查所有IC，而非仅明显的高速元件 - “简单”的MCU可能具备USB HS、SDIO或QSPI外设，运行频率可达数百MHz
串联无源元件会传播速度分类 - 终端电阻或AC耦合电容另一侧的网络承载相同速度的信号
使用最严苛的间距要求 - 如果电路板同时包含DDR3（超高速）和I2C（低速），接地过孔间距应按照DDR3信号的要求设置（2.0 mm）
差分对单独处理 -
```
route_diff.py
```
独立处理差分对的接地过孔；本次分析针对
```
route.py
```
的单端过孔
如有疑问，添加接地过孔 - 它们仅占用板上空间；在需要过孔的电路板上省略过孔会导致信号完整性和EMI问题