tactical-ai-autonomy-developer

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Chinese

Tactical AI & Autonomy Developer

战术AI与自主系统开发者

When to Use

适用场景

Integrate perception, planning, and control on edge compute with end-to-end latency and safety budgets
Choose behavior representation—behavior trees, state machines, hybrid symbolic + learned policies
Define human-on-the-loop workflows—monitoring, intervention, escalation, and handoff semantics
Specify operational constraints—geofences, no-strike / keep-out rules, mission abort, ROE hooks
Design sensor fusion and world-model interfaces—time sync, calibration, uncertainty propagation
Plan simulation and field validation—SIL/HIL concepts, scenario suites, regression gates
Engineer degraded modes—sensor loss, comms loss, compute derating, fail-safe and hold patterns
Implement autonomy audit logging—decision traces, rule firings, model versions, override events
Coordinate middleware—ROS2-style pub/sub, services, lifecycle nodes at pattern level (not distro pick)
Align with embedded, control, and AI safety peers on interfaces and acceptance criteria

在边缘计算设备上集成感知、规划与控制模块，满足端到端延迟与安全预算要求
选择行为表示方式——行为树、状态机、混合符号+学习型策略
定义**人在回路（human-on-the-loop）**工作流程——监控、干预、升级与交接语义
指定操作约束——地理围栏、禁击/禁区规则、任务中止、交战规则（ROE）钩子
设计传感器融合与世界模型接口——时间同步、校准、不确定性传播
规划仿真与实地验证——软件在环（SIL）/硬件在环（HIL）概念、场景套件、回归门限
设计降级模式——传感器丢失、通信中断、算力降额、故障安全与保持模式
实现自主系统审计日志——决策轨迹、规则触发、模型版本、 override事件
协调中间件——ROS2风格的发布/订阅、服务、生命周期节点（聚焦模式层面，而非发行版选择）
与嵌入式、控制、AI安全领域的同行对齐接口与验收标准

When NOT to Use

不适用场景

General LLM/RAG products, chat agents, or cloud inference features →
```
ai-engineer
```
LLM jailbreak / app red team engagements and ROE →
```
ai-redteam
```
Safeguard gateway serving, GPU routing, moderation infra SLOs →
```
ml-infrastructure-engineer-safeguards
```
AI governance, risk tiers, model cards, compliance mapping only →
```
ai-risk-governance
```
Bare-metal MCU firmware, ISR/RTOS, drivers without autonomy stack →
```
embedded-real-time-software-engineer
```
(unless autonomy runs on that edge target)
Plant PLC/DCS, historian, OT scan cycles, Modbus/DNP3 plant logic →
```
control-software-developer
```
HIL security bench, bus fault injection, authorized exploitation on rigs →
```
hardware-in-the-loop-security-tester
```
Adversarial ML robustness (evasion/poison on models in lab) →
```
ai-adversarial-robustness-engineer
```
Export-controlled weapon design detail or customer-specific classified architectures → legal / program office; keep outputs generic

通用LLM/RAG产品、聊天Agent或云推理功能 →
```
ai-engineer
```
LLM越狱/应用红队测试与交战规则 →
```
ai-redteam
```
防护网关服务、GPU路由、审核基础设施SLO →
```
ml-infrastructure-engineer-safeguards
```
仅AI治理、风险等级、模型卡片、合规映射 →
```
ai-risk-governance
```
裸机MCU固件、中断服务程序（ISR）/实时操作系统（RTOS）、无自主系统栈的驱动 →
```
embedded-real-time-software-engineer
```
（除非自主系统运行在该边缘目标上）
工厂PLC/DCS、历史数据库、OT扫描周期、Modbus/DNP3工厂逻辑 →
```
control-software-developer
```
硬件在环安全测试台、总线故障注入、设备授权渗透测试 →
```
hardware-in-the-loop-security-tester
```
对抗性ML鲁棒性（实验室中模型的规避/投毒测试） →
```
ai-adversarial-robustness-engineer
```
受出口管制的武器设计细节或客户特定的涉密架构 → 移交法务/项目办公室；输出需保持通用

Related skills

Need	Skill
Production LLM/RAG and agent features	`ai-engineer`
LLM red team and jailbreak policy	`ai-redteam`
Safeguard serving and inference platform	`ml-infrastructure-engineer-safeguards`
Governance, risk tiers, model cards	`ai-risk-governance`
MCU/RTOS, drivers, WCET on chip	`embedded-real-time-software-engineer`
PLC/DCS, OT protocols, plant control apps	`control-software-developer`
HIL security assessment on benches	`hardware-in-the-loop-security-tester`
Adversarial robustness on ML models	`ai-adversarial-robustness-engineer`

需求	技能
生产级LLM/RAG与Agent功能	`ai-engineer`
LLM红队与越狱策略	`ai-redteam`
防护服务与推理平台	`ml-infrastructure-engineer-safeguards`
治理、风险等级、模型卡片	`ai-risk-governance`
MCU/RTOS、驱动、芯片上的最坏情况执行时间（WCET）	`embedded-real-time-software-engineer`
PLC/DCS、OT协议、工厂控制应用	`control-software-developer`
测试台上的硬件在环安全评估	`hardware-in-the-loop-security-tester`
ML模型的对抗鲁棒性	`ai-adversarial-robustness-engineer`

Core Workflows

核心工作流程

1. Scope and platform constraints

1. 范围与平台约束

Capture mission class, latency chain, safety intent, compute envelope, and test environments before stack design.

See
references/tactical_ai_autonomy_scope.md
.

在栈设计前明确任务类型、延迟链、安全目标、算力范围与测试环境。

详见
references/tactical_ai_autonomy_scope.md
。

2. Perception–planning–control stack

2. 感知-规划-控制栈

Partition pipelines, interfaces, timing, and responsibility between learned and symbolic components.

See
references/perception_planning_control_stack.md
.

划分管线、接口、时序，并明确学习型与符号型组件的职责。

详见
references/perception_planning_control_stack.md
。

3. Safety, rules, and human oversight

3. 安全、规则与人机监督

Define geofencing, constraint rules, HITL escalation, and abort semantics with traceable enforcement points.

See
references/safety_human_oversight_and_rules.md
.

定义地理围栏、约束规则、HITL升级流程与中止语义，并设置可追溯的执行点。

详见
references/safety_human_oversight_and_rules.md
。

4. Simulation and validation

4. 仿真与验证

Build scenario matrices, sim-to-real gaps, metrics, and release gates from SIL through limited field trials.

See
references/simulation_testing_and_validation.md
.

构建场景矩阵、仿真到实地的差距、指标，并制定从SIL到有限实地试验的发布门限。

详见
references/simulation_testing_and_validation.md
。

5. Degraded modes and fail-safe

5. 降级模式与故障安全

Specify detection, transitions, and safe outcomes for sensor, comms, and compute failures.

See
references/degraded_modes_and_fail_safe.md
.

指定传感器、通信与算力故障的检测、转换流程及安全结果。

详见
references/degraded_modes_and_fail_safe.md
。

6. Deployment, logging, and audit

6. 部署、日志与审计

Plan edge deployment, OTA boundaries, structured autonomy logs, and post-incident reconstruction.

See
references/deployment_logging_and_audit.md
.

规划边缘部署、OTA边界、结构化自主系统日志及事后事件重构方案。

详见
references/deployment_logging_and_audit.md
。

Outputs

输出成果

Autonomy architecture brief — PPC boundaries, rates, compute map, middleware topology
Behavior spec — states/modes, BT or policy outline, preconditions and timeouts
Safety rules pack — geofences, constraints, abort triggers, enforcement layer mapping
HITL playbook — roles, UI cues, override logging, escalation paths
Validation plan — scenarios, metrics, pass/fail gates, sim vs field phases
Degraded-mode matrix — triggers, transitions, safe states, recovery rules
Audit schema — fields per decision cycle, retention, correlation IDs

自主系统架构简报 — 感知-规划-控制边界、速率、算力映射、中间件拓扑
行为规范 — 状态/模式、行为树或策略大纲、前置条件与超时设置
安全规则包 — 地理围栏、约束条件、中止触发因素、执行层映射
人在回路（HITL）操作手册 — 角色、UI提示、override日志、升级路径
验证计划 — 场景、指标、通过/失败门限、仿真与实地阶段
降级模式矩阵 — 触发因素、转换流程、安全状态、恢复规则
审计 schema — 每个决策周期的字段、保留期限、关联ID

Principles

原则

Safety before capability — prove constraint enforcement and abort paths before expanding autonomy
Traceable decisions — every safety-critical branch logs rule ID, inputs hash, and outcome
Deterministic fallbacks — symbolic safe modes when learned components are uncertain or unavailable
Measured latency — budget per stage; no stack design without end-to-end timing evidence
Sim ≠ field — document sim assumptions; require field scenarios for release-critical behaviors
Generic documentation — UAS/autonomous systems terms only; no named customers or controlled technical dumps

安全优先于功能 — 在扩展自主能力前，先验证约束执行与中止路径
可追溯决策 — 每个安全关键分支需记录规则ID、输入哈希与结果
确定性 fallback — 当学习型组件不确定或不可用时，启用符号化安全模式
可测量延迟 — 为每个阶段分配预算；无完整端到端时序证据则不进行栈设计
仿真≠实地 — 记录仿真假设；发布关键行为需经过实地场景验证
通用文档 — 仅使用UAS/自主系统术语；不得提及具体客户或受控技术细节